There is a strong demand in recent years for high-density integration and high-density mounting of electronic components such as semiconductor chips because of the desire for high performance and reduction in weight and size of electronic apparatuses such as portable data terminals, and that this is driving a further advancement of semiconductor packages toward miniaturization and multiplication of terminal pins for use as electronic components for such apparatuses. It has now come close to the limit of miniaturization of semiconductor packages in the conventional configuration of using lead frames.
For the above reason, surface-mounted semiconductor packages such as BGA (“Ball Grid Array”) and CSP (“Chip Scale Package”) have recently become the main stream of the components comprised of semiconductor chips mounted on circuit boards.
For semiconductor packages of these kinds, the wire bonding method, the TAB (“Tape Automated Bonding”) method, and the FC (“Flip Chip”) bonding method are some of the methods known for electrically connecting semiconductor chips with terminals of a substrate comprised of electrodes and conductor traces.
Numerous ideas have been shown of the BGA and CSP structures using the FC bonding method since it is especially advantageous for miniaturizing semiconductor packages.
For example, the FC bonding method, in general, is a method in which protruding electrodes called bumps are formed in advance on electrodes of a semiconductor chip, and the bumps and terminals on a substrate are connected by thermo-compression while they are aligned in positions.
Electrolytic plating and stud bumping are among a number of the methods used to form bumps beforehand on semiconductor chips. There is a shortcoming in the method of forming bumps by electrolytic plating, that it takes a considerable time and cost for the processing since the bumps need to be formed only of a solder material into the desired size. On the other hand, electrolytic plating causes variations in the size of formed bumps because it is difficult to produce a perfectly uniform distribution of electric current inside a plating tank. In the method of forming bumps only of a solder material, it is also difficult to alleviate the problems of processing time and cost since the variations in the size of the bumps become larger as the time of plating increases. There is also a new method developed to form bumps having metallic cores made of such a material as copper, for instance, in order to ensure reliability of bonded portions of the bumps against humidity. However, it further increases the cost of processing for such reasons as making the forming steps more complex.
On the other hand, the stud bumping is a method of forming bumps by bonding gold wires onto electrodes of a semiconductor chip and cutting them. This method takes a considerable time to process since the bumps are formed one by one on the electrodes of the semiconductor chip. It also has a shortcoming of high cost of manufacturing due to a high price of the gold wires used for the bumps.
A bump transfer method has been developed, in which a batch of bumps are formed at once on electrodes of semiconductor chips in order to solve the above shortcoming. In this method, a bump transfer sheet provided with solder bumps formed on a sheet base is positioned in alignment with the semiconductor chips, and all the bumps on the bump transfer sheet are transferred at once to the semiconductor chips by heat and compression. These methods are disclosed in Japanese Patent Unexamined Publications, Nos. H05-166880 (hereinafter referred to as “patent document 1”) and H09-153495 (“patent document 2”), for example.
There is also another technique of composing solder bumps having copper cores to ensure reliability of bonded portions to the solder against humidity, and transferring the batch of bumps at once, as disclosed, for example, in Japanese Patent Unexaminied Publication, No. 2000-286282 (“patent document 3”).
The bumps disclosed in the patent documents 1 and 2 have problems, however, as described hereinafter with reference to FIG. 21A to FIG. 21C.
That is, bumps 1800 are formed into spherical shapes by the surface tension of solder on electrodes 1820 of substrate 1810, as shown in FIG. 21A. This gives rise to a problem that shapes of bumps 1800 vary (especially in their height) if amounts of the solder before being melted are not consistent, or when the electrodes are formed in a variety of area sizes.
In addition, since bumps 1800 have spherical shapes, they become barrel shapes 1850 when bonded to bonding electrodes 1840 of electronic component 1830, as shown in FIG. 21B. This produces a concentration of stresses on the bonded portions of bumps 1800 with bonding electrodes 1840, and thereby giving rise to another problem of causing separations, cracks and the like failures in the interfaces with bonding electrodes 1840.
Moreover, because of barrel shapes 1850 of bumps 1800, there is a possibility of short-circuiting 1860 between adjoining bumps 1800, as shows in FIG. 21C, which prevents electrodes 1820 from being formed in narrow pitches. Bonding electrodes 1820 of finer pitches may be possible by reducing the size of bumps 1800. However, it is difficult for bumps of smaller sizes to ensure the reliability of connections since they cannot tolerate warping of electronic component 1830 such is a semiconductor chip.
In the case of the solder bumps shown in the above patent document 3, conductive terminals comprised of metal layers and solder layers laminated on a transfer sheet are heated and compressed to bond them with solder layers on bonding electrodes of a semiconductor chip or the like component. The solder layers are then melted, and the transfer sheet removed when the metal layers are wetted throughout with migrated solders to complete a batch processing of the bumps. However, this method also has a problem of forming fine bumps because the melted solder layers tend to increase sizes of the bumps. In addition, it is also difficult to melt the metal layers of copper, for instance, to complete the bonding if the metal layers are not entirely wetted due to insufficient flow of the melted solder layers, which hence impairs reliability of the connections.
The conductive terminals are formed by the steps of coating a resin layer Serving as the transfer sheet on a copper foil, placing a dry film on the copper foil after the resin is hardened, exposing, developing, and forming a solder layer thereafter by electrolytic plating. The dry film is then removed and the copper foil is etched to form the conductive terminals of a pillar shape. This method thus makes the manufacturing process complex, and has a drawback in view of the productivity and manufacturing cost. It also gives rise to a problem of treating waste fluid and the like substances since it requires an etching process.